Quiz 8
Question 1
Which of the following is caused by fetching the wrong (branch NOT taken) instruction into the pipeline during a branch instruction?
Control Hazard
Question 2
Which of the following is caused by not yet reaching the write-back stage when an instruction is decoding the source registers?
RAW Hazard
Question 3
Which of the following pipeline stages reads and writes to RAM?
MEM
Question 4
Which of the following pipeline stages uses the ALU or FPU?
EXE
Question 5
Which of the following pipeline stages reads the source registers?
ID