Quiz 6
Question 1
Given the following value in memory, what is the size of the instruction?
0x87aa_45a9
16 bits
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Looking at the opcode for 0x87aa_45a9, we get 0b010_1001. We see that bits 1:0 are 0b01, meaning that this is a 16-bit instruction. All 32-bit instructions will have bits 1:0 = 0b11.Question 2
What type of instruction is given below?
jalr a0, -8(ra)
I-type
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JALR (jump-and-link-to-register) is an I-type instruction. The only J-type instruction we have is JAL since the upper 20 bits of the memory label need to be stored in the instruction. JALR does not have a memory label and uses a register to store the memory address instead, meaning we don't need a J-type to encode it.Question 3
Given the following object code instruction, what row and column (denoted ROW:COLUMN below) would I look at to determine the instruction category?
0xfeed_beef
3:3
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0xFEED_BEEF is the full instruction, but the opcode is the lower (rightmost) 7 bits, which are: 0b1[110_1111]. We also know that the lower (rightmost) two bits will always be 0b11 for a 32-bit sided instruction, so our 5-bit opcode is 11:011. The row comes first, which is row 3, then the column, which is column 3.Question 4
What type of instruction is given below?
beq a0, a1, label
B-type
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All branch instructions are encoded using B-type.Question 5
How many bits are required to store the shamt (shift amount) field for the SLLIW instruction?
5
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SLLIW is "shift left, logical WORD", meaning it only functions on the lower 32 bits of a 64-bit register. Since the valid shift amounts are 31:0, we need 5 bits to store that value (31 = 0b11111, 0 = 0b00000).Quetion 6
What type of instruction is given below?
mul a0, t0, s0
R-type
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mul has three registers: rd, rs1, and rs2, which is stored using an R-type instruction.Question 7
The first field the CPU will examine to determine the instruction type is which of the following?
opcode