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• Pipelining Practice
  • Question 1
  • Question 2
  • Question 3
  • Question 4
  • Question 5
  • Question 6
  • Question 7
  • Question 8
  • Question 9
  • Question 10

Pipelining Practice

Question 1

The load and store instructions require the EXE stage to

add the offset to the base

Question 2

The Memory stage will use the memory controller to load or store a value.

Question 3

The instruction decode pipeline stage will retrieve the operand values from the registers.

Question 4

The Instruction Fetch pipeline stage uses the PC to determine the instruction to run.

Question 5

The Instruction Decode pipeline stage is responsible for widening shorter immediates.

Question 6

The CPU being unable to decide whether to fetch one instruction or another best describes which of the following hazards?

control

Question 7

Order the pipeline stages below.

First stage

Instruction fetch

Instruction decode

Execute

Memory

Write-Back

Last stage

Question 8

Pipelining is the opposite of a single-cycle CPU, where instructions are fetched, decoded, and executed in one cycle of the clock timer.

Question 9

A/an branch predictor can be used to reduce the number of flushed pipelines due to the CPU loading the wrong instruction after a branch.

Question 10

operand forwarding will output the result of the ALU directly to the input of the ALU for the next instruction to avoid a RAW hazard.